I finally have an answer to my question! PleasingFungus from the #tigIRC channel on Esper discussed the question with me for two hours straight today and this is the answer I ended up with:

If a scalar (not superscalar) processor has multiple nonredundant functional units (a single FPU and a sin…

I spent most of the day trying to find the answer to the following question:

If a scalar (not superscalar) processor has multiple nonredundant functional units (a single FPU and a single ALU for example) and it issues an instruction to the FPU at a certain clock tick, could it issue another instr…

"Scoreboarding" is also called "Thornton's Algorithm". Tomasulo's Algorithm and Thornton's Algorithm were developed around the same time with roughly the same goals.

• They are both dynamic scheduling methods.
• They both resolve dependencies (RAW, WAR, and WAW).
• They are both pipelined.
• They both have …

Welp, I am still trying to figure out how an out-of-order scalar processor would work. The out-of-order execution part is easy enough, but I am having trouble figuring out how in-order completion would work. To this end, I am currently researching scoreboarding in the hopes of gleaning some h…

Today I was able to find an answer to the following research question:

Can a processor have out-of-order execution and in-order completion?
Yes; with one pipeline per active instruction. In other words, for every instruction in the active instruction window (every instruction which can be selected…

Today I was able to find answers to the following questions:

What is the reorder buffer?
It is a buffer which is used to ensure that instructions commit in-order. It is also used in one method of register renaming. There is one entry for every active instruction. An instruction is active after…

Unfortunately I was unable to get much research done today. However, I did learn a few things.

A processor can be either statically scheduled or dynamically scheduled.

A statically scheduled processor depends on the compiler to create the execution schedule. I am guessing this is either through hi…

Memory data hazards are prevented by keeping a list of all the addresses with outstanding stores, and putting a load into a queue if it is for an address in that list. I don't know how WAW hazards are prevented though... I am currently reading "ARB: A Hardware Mechanism for Dynamic Reordering…

Today I started reading about memory access. I don't really have much to say on the matter yet, except that it is apparently not as easy to execute multiple memory access instructions at once as it is for integer/float instructions. This mostly stems from the fact that until the instruction i…

Today I finally finished the section on instruction issuing. This took me a while because I had questions which didn't have readily available answers. Here are the questions I was attempting to find answers to, along with the answers I eventually found (if you have a better answer to any of t…